• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In a power converter according to the invention, each of the gate circuits (11 to 14) is designed in such a way that it detects a short-circuit current and sends a short-circuit signal to a blocking signal generating circuit (41) when the short-circuit current flows in a corresponding switching device (1 to 4), and that it blocks the short-circuit current flowing to the corresponding switching device (1 to 4) when a blocking signal is received from the blocking signal generating circuit (41), and the blocking signal generating circuit (41) is designed in such a way that it simultaneously sends a blocking signal to each of the gate circuits (11 to 14) sends when the short-circuit signal is received by any gate circuit of the gate circuits (11 to 14).
    公开号:CH716358A2
    申请号:CH00709/20
    申请日:2020-06-15
    公开日:2020-12-30
    发明作者:Matsumoto Shuhei；Ishizuki Teruyuki；Mori Junji
    申请人:Toshiba Kk；Toshiba Energy Systems & Solutions Corp；
    IPC主号:
    专利说明:

    AREA
    The embodiments described herein generally relate to a power converter.
    BACKGROUND
    In recent years, a high-voltage power converter that configures each branch by a series circuit connected in series with a plurality of semiconductor switching devices is increasingly used.
    If a short-circuit current is generated due to a failure of a part of a series-connected switching device, when each of the series-connected switching devices detects the short-circuit current independently and performs a power cut, the switching device that has cut the current first, an entire voltage lead, which can gradually lead to the destruction of the device.
    It is therefore desirable to provide a power converter that can switch off the short-circuit current so that some of the switching devices do not have to carry the entire voltage when a short-circuit current flows in the series-connected switching devices.
    SUMMARY
    According to one embodiment, a power converter is provided which has a plurality of switching devices which are connected in series in each branch; a plurality of gate circuits each provided in the plurality of switching devices; and a lock signal generation circuit communicating with the plurality of gate circuits, wherein each of the plurality of gate circuits is configured to detect a short-circuit current and send a short-circuit signal to the lock signal generation circuit when the short-circuit current flows in a corresponding switching device, and that it blocks the short-circuit current flowing to the corresponding switching device when a blocking signal is received from the blocking signal generating circuit, and the blocking signal generating circuit is configured to be able to receive each of the short-circuit signals output from the plurality of gate circuits and at the same time send an inhibit signal to each of the plurality of gate circuits when the short circuit signal is received by a gate circuit of the plurality of gate circuits.
    BRIEF DESCRIPTION OF THE DRAWINGS
    Fig. 1 is a diagram showing a configuration of a part of a power converter according to a first embodiment. FIG. 2 is a diagram showing a modification of the configuration of FIG. 1. Fig. 3 is a timing chart showing an example of the operation of short circuit protection. 4 is a diagram showing a configuration of part of a power converter according to a second embodiment. Fig. 5 is a diagram showing the configuration of part of a power converter according to a third embodiment. 6 is a diagram showing the configuration of part of a power converter according to a fourth embodiment. 7 is a diagram showing a configuration of part of a power converter according to a fifth embodiment.
    DETAILED DESCRIPTION
    The embodiments will be described with reference to the accompanying drawings.
    [First embodiment]
    A first embodiment will be described with reference to Figs.
    Fig. 1 is a drawing showing a configuration of a part of a power converter according to the first embodiment.
    The power converter according to the present embodiment is a device which is designed such that it converts current from direct current to alternating current, and the multiple semiconductor switching devices 1 to 4 (hereinafter referred to as "switching devices 1 to 4"), which in one Branch are connected in series, as well as a short-circuit protection circuit 20 which is mounted with a plurality of gate circuits 11 to 14, which are respectively assigned to the switching devices 1 to 4, and a short-circuit signal integration and locking signal generating circuit 41 (hereinafter referred to as "locking signal generating circuit 41") which can communicate with the gate circuits 11-14.
    Fig. 1 shows an example in which a number of switching devices and a number of gate circuits are each four; however, the present embodiment is not limited to such an example. For example, more switching devices and gate circuits may be provided than in this example.
    Each of the switching devices 1 to 4 includes, for example, an injection amplified gate transistor (IEGT) having high voltage resistance. However, the present embodiment is not limited to such an example.
    Each of the gate circuits 11 to 14 is designed such that it detects when a short-circuit current flows in a corresponding switching device, and that it generates a short-circuit current detection signal (hereinafter referred to as "short-circuit signal") that indicates that the Short-circuit current has been detected, sends to the locking signal generating circuit 41, and is also designed such that it performs a process of switching off the short-circuit current that flows to the corresponding switching device when a short-circuit current locking command signal (hereinafter referred to as "locking signal") is received, that instructs to block the short-circuit current from the blocking signal generating circuit 41.
    The locking signal generating circuit 41 is a circuit for integrating short-circuit signals, which are respectively output from the gate circuits 11 to 14, and for the simultaneous output of locking signals to the gate circuits 11 to 14. In particular, the locking signal generating circuit 41 is designed in such a way that that it is able to receive the short-circuit signals output from the gate circuits 11 to 14, respectively, and at the same time to send the lock signals to each of the gate circuits 11 to 14 when the lock-signal generation circuit 41 receives the short-circuit signal from any of the Gate circuits 11-14 receives.
    The gate circuit 11 includes a voltage detection circuit 31, a short-circuit detection circuit 32, and a gate signal generation circuit 33. Fig. 1 omits a detailed configuration of the gate circuits 12-14. Each of the gate circuits 12 to 14 includes a voltage detection circuit 31, a short-circuit detection circuit 32, and a gate signal generation circuit 33, which are the same as those of the gate circuit 11.
    The voltage detection circuit 31 detects a collector-emitter voltage (Vce) of the corresponding switching device and outputs voltage information indicating a detection result of Vce.
    The short-circuit detection circuit 32 detects a short-circuit flowing in the corresponding switching device current, and outputs the short-circuit signal to the lock signal generation circuit 41 based on the voltage information (Vce information) output from the voltage detection circuit 31. When a short circuit is caused by the failure of the device because a large current flows, it is possible to detect a short circuit current by monitoring the voltage, since the voltages at both terminals of the device will increase due to the characteristics of the device even though the device changes is in the ON state.
    The gate signal generation circuit 33 generates a gate signal for controlling a gate of the above corresponding switching device and performs a signal operation to cut off the short-circuit current flowing in the corresponding switching device when the lock signal is received from the lock signal generation circuit 41.
    The short-circuit signal output from the short-circuit detection circuit 32 of the gate circuit 11 is input to the lock signal generation circuit 41 through a communication line T1. The short-circuit signal output from an unillustrated short-circuit detection circuit 32 of the gate circuit 12 is input to the lock signal generation circuit 41 through a communication line T2. The short-circuit signal output from an unillustrated short-circuit detection circuit 32 of the gate circuit 13 is input to the inhibit signal generation circuit 41 through a communication line T3. The short-circuit signal output from a short-circuit detection circuit 32, not shown, of the gate circuit 14 is input to the inhibit signal generation circuit 41 via a communication line T4.
    Only one short-circuit protection circuit 20 mounted with the lock signal generation circuit 41 is provided for each branch.
    The lock signal output from the lock signal generation circuit 41 to the gate circuit 11 is input to the gate signal generation circuit 33 of the gate circuit 11 through a communication line S1. The lock signal output from the lock signal generation circuit 41 to the gate circuit 12 is input to the gate signal generation circuit 33 (not shown) of the gate circuit 12 through a communication line S2. The lock signal output from the lock signal generation circuit 41 to the gate circuit 13 is input to the gate signal generation circuit 33 of the gate circuit 13 through a communication line S3. The lock signal output from the lock signal generation circuit 41 to the gate circuit 14 is input to the gate signal generation circuit 33 of the gate circuit 14 through a communication line S4.
    The present embodiment shows an example of using the information of a collector-emitter voltage (Vce) of the switching device to detect a short-circuit current flowing in each switching device; however, the present illustration is not limited to such an example. The detection of a short-circuit current can be achieved by using other information than the aforementioned Vce (e.g. information about a gate charge (Qq), which is obtained by integrating a gate current (Ig) of the corresponding switching device, information about a gate-emitter Voltage (Vge), or information about a branch current flowing through a branch configured by individual switching devices).
    Consider a case where a short-circuit current flows in a branch configured by the switching devices 1 to 4 in the configuration shown in FIG. In this case, each voltage detection circuit 31 in the gate circuits 11 to 14 corresponding to the switching devices 1 to 4, respectively, detects a short-circuit current flowing in the corresponding switching device; however, the case is not limited to the simultaneous detection of a short-circuit current in all of the voltage detection circuits 31. The single voltage detection circuit 31 can detect the short-circuit current at different times, for example, the short-circuit current flowing in the switching device 1 is detected first, and the short-circuit current flowing in the switching devices 2, 3 and 4, respectively, is sequentially detected. In such a case, for example, the short-circuit signal output from the voltage detection circuit 31 of the gate circuit 11 may first be input to the inhibit signal generation circuit 41, and the short-circuit signal output from the respective voltage detection circuit 31 of the gate circuits 12, 13, 14 can be input to the lock signal generation circuit 41 sequentially.
    Even if the respective short-circuit currents are output from the gate circuits 11 to 14 at different times, the lock signal generating circuit 41 sends the lock signals to the respective gate circuits 11 to 14 at the same time and not at different times.
    With such a configuration, the gate signal generating circuit 33 of the respective gate circuits 11 to 14 inputs the lock signal at the same time and reduces the gate signal to lock the current of the corresponding switching device at the same time. In this case, each gate signal generating circuit 33 does not immediately change the state of the respective switching devices from gate ON to gate OFF and gradually changes from a state from gate ON to gate OFF by reducing a predetermined speed of the gate signal. When each of the switching devices 1 to 4 is in a gate OFF state at the same time and the current is blocked, the voltage Vce is at a normal voltage level.
    By configuring the power converter as shown in FIG. 1, the short-circuit current can be blocked so that some of the switching devices do not carry the entire voltage when the short-circuit current flows in the switching devices 1 to 4 connected in series.
    FIG. 2 is a diagram showing a modification example of the configuration shown in FIG. 1. In the configuration shown in FIG. 2, each of the gate circuits 11 to 14 in the configuration shown in FIG. 1 additionally includes an overvoltage protection circuit 34. However, this overvoltage protection circuit 34 is not a necessary circuit element and can be provided only when necessary.
    The overvoltage protection circuit 34 provided in each of the gate circuits 11 to 14 has a function of suppressing an increase in Vce of the switching device when the short-circuit current flowing to the corresponding switching device is blocked. In particular, the overvoltage protection circuit 34 includes the function of sending a voltage setting command (soft shutdown command) to a gate signal generating circuit 33, the voltage setting command instructing to reduce the Vce of the switching device at an even slower rate if the Vce of the switching device is during the shutdown of the to the corresponding switching device flowing short-circuit current exceeds a predetermined threshold (overvoltage protection operating threshold). When the voltage setting command is input to the gate signal generation circuit 33, the gate signal generation circuit 33 further slows down the level of the gate descending signal for a certain period of time. With such a configuration, a voltage rise due to a surge voltage can be suppressed and the corresponding switching device can be switched to the gate OFF state.
    By configuring the power converter as shown in Fig. 2, it is possible to suppress the rise of such a voltage in a state in which a certain switching device goes into an overvoltage state.
    An example of the operation of the short-circuit protection by a power converter according to the present embodiment is explained with reference to the timing diagram shown in FIG. In the present example, the mode of operation is explained using the example of the configuration from FIG. 2. Further, the explanation will focus on the relationship between a gate circuit of the gate circuits 11 to 14 (e.g., the gate circuit 11) and the lock signal generation circuit 41.
    In the present example, the information of a branch current (current information) is not used for the detection of the short-circuit current; however, the aspects relating to the current information are also explained in order to better explain the mode of operation.
    In the gate circuit 11, it is assumed, for example, that the gate signal generation circuit 33 supplies a gate signal of “gate voltage (Vge) = 0” to a gate of the switching device 1, and the switching device 1 is in the gate OFF state is located. In this case, no current flows in the branch and the current information shows a state "Branch current = 0". Further, the voltage information to be output from the voltage detection circuit 31 is indicated by “Vce = constant value (OFF state of normal voltage levels)”. In addition, both the short-circuit signal and the lock signal are in an OFF state, and the voltage setting command is also in an OFF state.
    When the gate signal of the gate signal generating circuit 33 of the gate circuit 11 switches the corresponding switching device 1 to a gate ON state, for example at time t1, the Vce displayed in the voltage information drops to a predetermined level. As can be seen from the reference character P1, the branch current indicated in the current information begins to increase. The Vce indicated in the voltage information is held at a predetermined level for a certain period of time. The branch current specified in the current information finally reaches a saturation state.
    If the Vce specified in the voltage information exceeds, for example, a predefined threshold (a short-circuit current detection threshold) at time t2, it is assumed that the short-circuit current is generated at the switching device 1 and the short-circuit signal is sent from the short-circuit detection circuit 32 to the blocking signal generation circuit 41 . A process similar to that of this gate circuit 11 is assumed later in the gate circuits 12-14.
    After the short-circuit current has been detected at time t2, as shown with reference symbol P2, the short-circuit signal from the gate circuit 11 is first input, for example, at time t3 into the blocking signal generating circuit 41, and at the same time blocking signals from the blocking signal generating circuit 41 are entered at once to the gate circuits 11-14. These inhibit signals are input to the gate signal generation circuit 33 of the gate circuits 11 to 14, respectively.
    When the lock signal is inputted to the gate signal generation circuit 33 of the respective gate circuits 11 to 14 at time t3, the gate signal of the corresponding switching device, as shown by the reference character P3, from each gate signal generation circuit 33 with a is reduced at a predetermined speed, and the corresponding switching device gradually changes from a gate ON state to a gate OFF state.
    For example, suppose that when the voltage information indicating the Vce starts increasing, the branch current indicated in the current information starts decreasing.
    If the Vce specified in the voltage information exceeds a predefined threshold value (overvoltage protection operation threshold value), for example at time t4, this is detected by the overvoltage protection circuit 34. In this case, as shown by reference character P4, the voltage setting command (soft shutdown command) instructing to decrease the Vce of the corresponding switching device at an even lower speed is sent from the overvoltage protection circuit 34 to the gate signal generating circuit 33 at time t5.
    When this voltage setting command is inputted to the gate signal generation circuit 33, as shown by reference character P5, the fall of the descending gate signal level simultaneously becomes even slower for a certain period of time due to an operation in the gate signal generation circuit 33. This means that a decrease in the branch current indicated in the current information also becomes slower.
    With such a configuration, a voltage rise due to a surge voltage is suppressed and the corresponding switching device is slowly switched to the gate OFF state.
    When a certain period of time elapses from time t5, the voltage setting command is sent, for example, at time t6, and as shown by reference symbol P6, the gate signal of the corresponding switching device is reduced by the gate signal generating circuit 33 again at the original predetermined rate , and the corresponding switching device is gradually shifted from a gate ON state to a gate OFF state.
    Finally, the Vce indicated in the voltage information becomes a normal voltage level when the current is blocked, since each of the switching devices 1 to 4 simultaneously goes into a gate OFF state.
    According to the first embodiment, the short-circuit current can be blocked by adopting the configuration shown in FIG. 1, so that some of the switching devices do not have to carry the entire voltage when short-circuit current flows in the switching devices 1 to 4 connected in series. Furthermore, by adopting the configuration shown in FIG. 2, it is possible to suppress the increase in voltage in a state in which a certain switching device is going into an overvoltage state.
    Further, in the present embodiment, the Vce information obtained by the voltage detection circuit 31 is used to detect the short-circuit current flowing to each switching device; Thus, the Vce information can be used for overvoltage prevention by inputting it to the overvoltage protection circuit 34 as shown in Fig. 2, and the overvoltage protection can be achieved with a simple configuration.
    [Second embodiment]
    Next, the second embodiment will be described with reference to FIG. Figs. 1 to 3 used in the above explanations are also used appropriately. In the following, explanations overlapping with the configuration of FIG. 2 in the first embodiment will be omitted, and the explanations will focus on the parts of the configuration that differ.
    Fig. 4 is a diagram showing a configuration of a part of the power converter according to the second embodiment.
    In the configuration shown in Fig. 2 according to the above first embodiment, the figure shows an example in which the locking signal generating circuit 41 is mounted on a short-circuit protection circuit 20 independent of the gate circuits 11 to 14; on the other hand, in the second embodiment, the lock signal generation circuit 41 is mounted on a gate circuit of the gate circuits 11-14. In the following, for example, it is assumed that the gate circuit 11 of Fig. 2 is the gate circuit mounted on the inhibit signal generating circuit 41, and such a gate circuit is called "a representative gate circuit 11 '". A circuit board of the representative gate circuit 11 'serves as a master circuit board, and the circuit groups 31 to 33 and the lock signal generation circuit 41 are mounted on the master circuit board.
    The other configurations and operations are similar to those of the first embodiment.
    According to the second embodiment, the short-circuit protection circuit 20 is unnecessary, and the installation of the circuit board for mounting the short-circuit protection circuit 20 is also unnecessary. This suppresses an increase in the installation area of the circuit and an increase in the manufacturing cost.
    [Third embodiment]
    Next, the third embodiment will be described with reference to FIG. Figs. 1 to 4 used in the above explanation are appropriately used. In the following, explanations overlapping with the configuration of FIG. 4 in the second embodiment will be omitted, and parts of the configuration that are different will mainly be explained.
    Fig. 5 is a diagram showing a configuration of a part of the power converter according to the third embodiment.
    The difference between the third embodiment and the configuration of Fig. 4 in the second embodiment are communication lines connecting between a lock signal generation circuit 41 and the gate circuits 12-14.
    In the third embodiment, the communication lines C1, C2, C3, C4, which form a feedback daisy chain, are arranged so that the chain runs from the lock signal generation circuit 41 to the lock signal generation circuit 41, sequentially through the gate circuits 12 14 through 14 except for the representative gate circuit 11 '.
    The short-circuit signal output from the not-shown short-circuit detection circuit 32 of the gate circuit 12 is input to the lock signal generation circuit 41 through the communication lines C2, C3, C4. The short-circuit signal output from the not-shown short-circuit detection circuit 32 of the gate circuit 13 is input to the lock signal generation circuit 41 through the communication lines C3, C4. The short-circuit signal output from the not-shown short-circuit detection circuit 32 of the gate circuit 14 is input to the lock signal generation circuit 41 through the communication line C4.
    The lock signal output from the lock signal generation circuit 41 to the gate circuits 12 to 14 is input to the not-shown gate signal generation circuit 33 of the gate circuit 12 through the communication line C1; the signal is then input to the gate signal generating circuit 33 (not shown) of the gate circuit 13 via the communication line C2; and the signal is then input to the not-shown gate signal generating circuit 33 of the gate circuit 14 via the communication line C3.
    In the above configuration, when there occurs some time difference in an arrival time of the inhibit signals to the gate circuits 12 to 14, it is desirable to set a response speed of the not-shown gate signal generation circuit 33 in the gate circuits 12 to 14 so that that the disconnection of the short-circuit signals in each switching device is carried out simultaneously.
    The other configurations and operations are similar to those of the second embodiment.
    According to the third embodiment, the number of communication lines is reduced, and the area for setting the communication lines and the cost can also be reduced.
    [Fourth embodiment]
    Next, the fourth embodiment will be described with reference to FIG. Figs. 1 to 5 used in the foregoing explanation are appropriately used. In the following, explanations overlapping with the configuration of FIG. 2 in the first embodiment will be omitted, and the explanation will focus on the parts of the configuration that are different.
    Fig. 6 is a diagram showing a configuration of a part of a power converter according to a fourth embodiment.
    The difference between the fourth embodiment and the configuration of FIG. 2 in the first embodiment is a wireless communication path 50 provided for each of the communication lines T1 to T4 and S1 to S4 and the lock signal generation circuit 41 having the gate circuits 11 to 14 connects.
    Both the lock signal generation circuit 41 and the gate circuits 11 to 14 each transmit a short circuit signal or a lock signal via the wireless communication path 50.
    The other configurations and operations are similar to those of the first embodiment.
    According to the fourth embodiment, it is possible to switch between a connection state and a non-connection state of the communication via the wireless communication path 50; this improves the functionality during manufacture and assembly as well as the maintenance time. For example, it is possible to manufacture and test the lock signal generating circuit 41 before setting the power converter at a place of use in a factory, etc., and to transport and assemble the power converter to the place of use. In addition, it is possible to remove the short-circuit protection circuit 20 including the blocking signal generation circuit 41 from the power converter during maintenance work, etc., in order to carry out a single test, etc.
    [Fifth embodiment]
    Next, the fifth embodiment will be described with reference to FIG. Figs. 1 to 6 used in the foregoing explanation are appropriately used. In the following, explanations overlapping with the configuration of FIG. 2 in the first embodiment will be omitted, and the explanations will focus on the parts of the configuration that differ.
    Fig. 7 is a diagram showing a configuration of a part of a power converter according to the fifth embodiment.
    The difference between this fifth embodiment and the configuration of FIG. 2 in the first embodiment is that the power converter further includes, for each branch, one or more current detectors 35 which are provided in one of several lines which the switching devices 1 to 4 in series (for example, in a line connecting the switching device 1 to the switching device 2), and the short-circuit detection circuit 32 uses "current information" which is a current detection result from the current detector 35, and does not use "voltage information" which a voltage detection result of the voltage detection circuit 31 indicates.
    In other words, the short-circuit detection circuit 32 provided in each of the gate circuits 11 to 14 detects a short-circuit current when the short-circuit current flows in the corresponding switching device, and outputs the short-circuit signal to the lock signal generation circuit 41 based on the “current information “Which is the current detection result from the current detector 35. In particular, if the current value displayed in the current information exceeds a predefined threshold (short-circuit detection threshold), it is assumed that short-circuit current is generated at the corresponding switching device, and the short-circuit signal from the short-circuit detection circuit 32 is sent to the blocking signal generation circuit 41.
    The other configurations and operations are similar to the first embodiment.
    According to the fifth embodiment, a current flowing to each switching device can be detected directly by the current detector 35; thus the short-circuit current can be detected quickly and with high accuracy.
    (Miscellaneous)
    The above fifth embodiment shows the example in which the current detector 35 is provided for the configuration of FIG. 2 of the first embodiment and the short-circuit detection circuit 32 uses the “voltage information” instead of the “current information” to detect the short-circuit current. Other configurations such as the configuration of FIG. 4 according to the second embodiment, the configuration of FIG. 5 according to the third embodiment, and the configuration of FIG. 6 according to the fourth embodiment can also be configured to provide the current detector 35, and can be configured so that the short-circuit detection circuit 32 uses the “current information” instead of the “voltage information” to detect the short-circuit current.
    As explained above, according to each embodiment, when the short-circuit current flows in the switching devices connected in series, the short-circuit current can be blocked so that some of the switching devices do not carry the entire voltage.
    While certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein can be represented in a variety of other forms; in addition, various omissions, substitutions, and changes may be made in the form of the embodiments described herein. The accompanying claims and their equivalents are intended to cover such forms or changes that would come within the scope of the inventions.
    权利要求:
    Claims (7)
    [1]
    1. A power converter comprising:a plurality of switching devices (1 to 4) connected in series in each branch;a plurality of gate circuits (11 to 14) each provided in the plurality of switching devices (1 to 4); anda lock signal generation circuit (41) which can communicate with the plurality of gate circuits (11 to 14),wherein each of the plurality of gate circuits (11 to 14) is designed such that it detects a short-circuit current and sends a short-circuit signal to the blocking signal generation circuit (41) when the short-circuit current flows in a corresponding switching device (1 to 4), and that it the Short-circuit current flowing to the corresponding switching device (1 to 4) blocks when a blocking signal is received from the blocking signal generating circuit (41), andthe lock signal generation circuit (41) is configured to be able to receive each of the short-circuit signals output from the plurality of gate circuits (11 to 14) and at the same time to supply a lock signal to each of the plurality of gate circuits (11 to 14) transmit when the short-circuit signal is received from any gate circuit of the plurality of gate circuits (11 to 14).
    [2]
    The power converter according to claim 1, wherein each of the plurality of gate circuits (11 to 14) further comprises an overvoltage protection circuit (34) for suppressing a rise in a collector-emitter voltage of the switching device (1 to 4) when connected to the corresponding one Switching device (1 to 4) flowing short-circuit current is blocked.
    [3]
    The power converter according to claim 1 or 2, wherein the lock signal generation circuit (41) is disposed on a circuit board of a representative gate circuit of the plurality of gate circuits (11-14).
    [4]
    4. The power converter according to claim 3, further comprising communication lines (S2-S4, T2-T4, C1-C4) which are sequentially connected from the lock signal generation circuit (41) via a plurality of the gate circuits other than the representative gate circuit to the lock signal generation circuit ( 41) arrive,wherein both the lock signal generating circuit (41) and the plurality of gate circuits except for the representative gate circuit transmit the short circuit signal or the lock signal via the communication lines (S2-S4, T2-T4, C1-C4).
    [5]
    The power converter of claim 1 or 2, wherein each of the lock signal generation circuit (41) and the plurality of gate circuits (11-14) transmit the short circuit signal or the lock signal via a wireless communication path (50).
    [6]
    6. The power converter of any one of claims 1 to 5, wherein each of the plurality of gate circuits (11 to 14):a voltage detection circuit (31) for detecting the collector-emitter voltage of the respective switching devices (1 to 4), anda short-circuit detection circuit (32) for detecting the short-circuit current and for sending the short-circuit signal to the locking signal generating circuit (41) when the short-circuit current flows in the corresponding switching device (1 to 4), based on a detection result of the voltage detection circuit (31),includes.
    [7]
    7. The power converter of any one of claims 1 to 5, further comprising:at least one current detector (35) which is provided for any one of a plurality of lines in order to connect the plurality of switching devices (1 to 4) in series,wherein each of the plurality of gate circuits (11 to 14) a short-circuit detection circuit (32) for detecting the short-circuit current and for sending the short-circuit signal to the locking signal generating circuit (41) when the short-circuit current flows in the respective switching devices (1 to 4), based on a Detection result of the current detector (35),includes.
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    同族专利:
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    JP2021005913A|2021-01-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP2019117085A|JP2021005913A|2019-06-25|2019-06-25|Power conversion device|
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